Move into semiconductor packaging with a day of training from Intel, ASE and Georgia Tech.
Twelve in-person courses at IEEE-IDSPS 2026 cover package design, substrates, assembly, power modules, thermal management and electrical test. Register through Cemetrix for 25% off, or come with colleagues and save up to 40%.
- When
- Sunday, December 6, 2026, 9:00 AM to 6:15 PM
- Where
- Novotel Visakhapatnam, Beach Road
- Format
- 3 tracks, four 2-hour courses in each
- Deadline
- Thursday, December 3
Interest registered
Thanks. The Cemetrix team will call you on your WhatsApp number.
Questions now? Call or WhatsApp +91 63811 94585.
How it works
You tell us what you need, and we handle the registration with IEEE-IDSPS.
Register interest
Tell us your track and whether colleagues will join you.
Talk to us
We confirm the fee, any group rate and how to pay.
Attend
Join the courses on December 6 and collect your certificate.
Pricing
The IEEE-IDSPS website gives 20% off. Registering through Cemetrix starts at 25% off, and groups save up to 40%.
| Per person | IEEE-IDSPS website (20% off) | Cemetrix, 1 to 4 people (25% off) | Cemetrix, group of 5+ (30% off) | Cemetrix, group of 10+ (40% off) |
|---|---|---|---|---|
| Working professional | ₹4,500 | ₹4,200 | ₹3,600 |
Group rates apply to colleagues from the same company registered together. For a team, see the Company page.
The courses
Choose one room for the day. Each runs four 2-hour courses taught by engineers and researchers who build advanced packages.
| Time | Room 1Design | Room 2Materials and substrates | Room 3Assembly, test, thermal and power |
|---|---|---|---|
| 9:00 to 11:00 AM | What is packaging? Why advanced packaging is importantProf. Madhavan Swaminathan, Penn State, USA | Advanced package substrates: ceramic, organic and glassDr. Venky Sundaram and Dr. Habib Hichri | IC assembly: wire bond, flip chip, TCB and hybrid bondingVikas Gupta, ASE, USA |
| 11:00 to 11:15 AM: tea and coffee | |||
| 11:15 AM to 1:15 PM | Package design and architecturesDr. Arun Chandrashekar, Intel, India | 2.5D interposers and RDLDr. Habib Hichri and Dr. Venky Sundaram | Power electronicsProf. Alan Mantooth, University of Arkansas, USA |
| 1:15 to 2:00 PM: lunch | |||
| 2:00 to 4:00 PM | Design for reliabilityProf. Abhijit Dasgupta, University of Maryland, USA | Packaging materials for power componentsProf. Raj Pulugurtha, Florida International University, USA | Thermal management of logic and power devicesProf. Yogendra Joshi, Georgia Tech, USA |
| 4:00 to 4:15 PM: tea and coffee | |||
| 4:15 to 6:15 PM | Power module designDr. Devan Iyer, GEA, USA | Opto-electronicsDr. Ravi Mahajan, Intel, USA | Electrical testProf. Abhijit Chatterjee, Georgia Tech, USA |
Why engineers attend
For electronics, electrical, mechanical, materials and test engineers who want to work in semiconductors or are already there.
Skills employers ask for
Packaging, 2.5D/3D integration, power modules, thermal and test, in one day.
Certificate
A certificate of participation for the courses you attend.
The right contacts
Speakers from Intel, ASE, GEA and leading US universities in the room.
Lower price
₹4,500 through Cemetrix, compared with ₹4,800 on the IEEE-IDSPS website.
Teaching on December 6: Intel, ASE, GEA, Ajinomoto Fine-Techno, Penn State, Georgia Tech, University of Maryland, University of Arkansas and Florida International University.
Questions
How much does it cost?
₹4,500 through Cemetrix, compared with ₹4,800 on the IEEE-IDSPS website. Groups of 5 or more from one company pay ₹4,200 each, and groups of 10 or more pay ₹3,600 each.
Can my company pay?
Yes. We can invoice your company directly. Mention it on the call, or ask your manager to use the Company page.
Is registering interest the same as registering?
No. Your seat is confirmed only after we speak with you and your registration is complete.
When is the last date?
Register interest by Thursday, December 3, so we can confirm your seat before December 6.
Seats in each room are limited.
Register interest